A synchronous SRAM (static random access memory) is typically used as a high speed cache in a data processing system. When being used as a cache, the synchronous SRAM is under the control of a single system clock. The system clock is used to generate one or more internal clock signals that are used to control the timing of the read and write operations of the synchronous SRAM.
FIG. 1 illustrates in block diagram form, prior art synchronous SRAM 10. SRAM 10 includes memory cell array 11. Array 11 is organized in a plurality of rows and columns, and is subdivided into blocks 12-17. Memory cell 46 is shown in block 12, and memory cell 47 is shown in block 17. Memory cells 46 and 47 are representative of the memory cells of array 11. Memory cell 46 is coupled to a bit line pair labeled "BL.sub.2 " and "BL.sub.2 *", and to a word line labeled "WL.sub.2 ". Memory cell 47 is coupled to a bit line pair labeled "BL.sub.1" and "BL.sub.1 *", and to a word line labeled "WL.sub.1 ". The bit line pairs are commonly used for both reading data from, and writing data into, the memory cell. The memory cells of array 11 are addressable through row decoding and column decoding. Row decoding includes address registers/predecoders 41 and row select 42. Column decoders 25 include address registers/predecoders 45 and local column decoders 26-31, which couple a bit line pair to a sense amplifier. A block of sense amplifiers 32 includes shared sense amplifiers 33-38. Each memory cell has a unique address at an intersection of a row and a column. Note that an asterisk (*) after a signal name indicates that the signal is a logical complement of a signal having the same name but lacking the asterisk.
To read a data bit from memory cell 47, a row address labeled "ROW ADDRESS" and a column address labeled "COLUMN ADDRESS" are provided to memory 10. The application of the addresses are timed by clock signal CLK.sub.1. Row select 42 provides a row select signal labeled "RS.sub.1 " to word line drivers 24. Word line drivers 24 select word line WL.sub.1. A predecoded column address PREDECODED COLUMN ADDRESS is provided to column decoders 25. Local column decoders 31 couples bit line pair BL.sub.2 and BL.sub.1 * to shared sense amplifiers 38. The data bit exists as a relatively small differential voltage on the pair of complementary bit lines. A sense amplifier from shared sense amplifiers 38 detects and amplifies the differential voltage and communicates it to output data multiplexer 43 as global data line signals GDL/GDL*, via read global data lines 40. Data register/buffer 44 receives a data signal corresponding to the data bit and latches it in response to clock signal CLK.sub.2.
To read a different data bit, such as memory cell 46, the same sequence of events occurs as when reading from memory cell 47, except that an address causes row select signal RS.sub.2 to select word line WL.sub.1, and local column decoder 26 to couple bit line pair BL.sub.1 and BL.sub.1 * to shared sense amplifiers 33. Row select signal RS.sub.2 must travel the length of array 11 to select word line WL.sub.1, and global data line signals GDL/GDL* must travel along global data lines 40 for the length of array 11. As a result, the access time for memory cell 46 is longer than the access time to memory cell 47. For synchronous memories that have a relatively small array size, or relatively slow clock cycle time, different access times to different parts of the array are not a problem. But in very large arrays that have very fast clock cycle times, the difference in access time to different parts of the array may cause unacceptable data signal skewing, which results from increased propagation delay from distant cells, that results in less timing margin for output data multiplexer 43 for a given clock period, and limits the speed at which the output clock CLK.sub.2 can operate. The data signal skewing problem becomes even worse as the size of the memory cell array is increased, or as higher clock speeds are demanded.
Some integrated circuit memories which use a technique known as revolutionary pinout have input/output circuitry on both sides of the array of the memory cells allowing for shorter data paths and faster access times. However, as memory arrays become large and clock speeds increase, the revolutionary pinout technique does not completely solve the data signal skewing problem.